1. Field of the Invention
The present invention relates to a phase detector for use in a phase locked loop circuit (PLL circuit) and the like which can operate at a high rate even with a low voltage.
2. Related Background Art
A PLL circuit can output a high-precision clock signal with a little frequency fluctuation, and can be constituted by combining a MOS transistor. Therefore, the circuit can broadly be used as a circuit, incorporated in a digital LSI chip, for generating a system clock of CPU, and the like.
The PLL circuit generates a clock signal having the same phase as that of a reference clock signal supplied from the outside. A phase detector for comparing the phase of the reference clock signal with that of the output clock signal of the PLL circuit and outputting a signal in accordance with a phase difference is disposed inside the PLL circuit.
FIG. 10 is a circuit diagram showing an internal constitution of a conventional phase detector. The phase detector of FIG. 10 comprises two set-reset flip-flops (hereinafter referred to as S-R flip-flops) 21 and 22 each including two NAND gates, NAND gate G21 to G25, and inverters IV21 and IV22.
When an output of the NAND gate G21 has a low level, the S-R flip-flop 21 is brought to a set state. When the output of the NAND gate G24 has the low level, the S-R flip-flop 22 is in the set state. Moreover, when the output of the NAND gate G23 has the low level, both the S-R flip-flops 21 and 22 are brought to a reset state.
FIG. 11 is an operation timing diagram of the phase detector of FIG. 10. An operation of the phase detector of FIG. 10 will be described hereinafter with reference to FIG. 11. In an initial state (before time t0), an output UPN of the NAND gate G22 has a high level, and an output RESETn of the NAND gate G23 also has the high level. When a reference clock REFCLK has the high level at the time t0, an output LC1 of the NAND gate G21 has the low level. Thereby, an output LO1 of a NAND gate G26 in the S-R flip-flop 21 reaches the high level, and an output LI1 of a NAND gate G27 reaches the low level.
Thereafter, when a clock signal CLK reaches the high level at time t1, an output LC2 of the NAND gate G24 reaches the low level, subsequently an output L02 of a NAND gate G28 in the S-R flip-flop 22 reaches the high level, and an output LI2 of a NAND gate G29 reaches the low level.
Thereafter, when the reference clock REFCLK reaches the low level at time t2, the output LC1 of the NAND gate G21 reaches the high level, subsequently the output UPN of the NAND gate G22 reaches the low level, and an output UP of the inverter IV21 reaches the high level.
Subsequently, when the clock signal CLK reaches the low level at time t3, the output LC2 of the NAND gate G24 has the high level. Thereby, the output RESETn of the NAND gate G23 reaches the low level, subsequently the output UPN of the NAND gate G22 reaches the high level, and the output UP of the inverter IV21 reaches the low level.
Thereafter, when the reference clock signal REFCLK reaches the high level at time t4, an operation of time t1 to t4 is repeated.
In FIG. 10, a time difference between when the output UPN of the NAND gate G22 reaches the high level at a falling of the clock signal CLK and when the reference clock signal REFCLK rises to start initialization of the next clock cycle is assumed to be Δt31. Then, the larger a phase delay time Δt11 of the clock signal CLK with respect to the reference clock signal REFCLK is, the smaller Δt31 becomes.
When frequencies of the reference clock signal REFCLK and clock signal CLK increase, Δt31 decreases and approaches zero. When Δt31 indicates a negative value, and when the reference clock signal REFCLK rises in the next clock cycle, the output UPN of the NAND gate G22 remains at the low level, the output LC1 of the NAND gate G21 cannot be set to the low level, and normal operation is not realized.
That is, a maximum operation frequency of the conventional phase detector shown in FIG. 10 is defined by the clock frequency at which Δt11 increases and Δt31 becomes zero. In a conventional example, when a phase delay of the clock signal CLK is large with respect to the reference clock signal REFCLK, a timing margin from a point of definition of the signal UPN as a previous signal of the signal UP until rising of the reference clock signal REFCLK at a start point of the next cycle is reduced. Therefore, the maximum operation frequency is lowered.
An example in which the phase delay of the clock signal CLK is large with respect to the reference clock signal REFCLK has been described above. However, the similar problem even occurs when the phase delay of the clock signal CLK is small with respect to the reference clock signal REFCLK. In this case, the circuit is initialized not with the reference clock signal REFCLK but with the rising of the clock signal CLK.